This application is based upon Japanese Patent Application No. 2000-383440 filed on Dec. 18, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device which has a super junction structure.
2. Related Art
A vertical type MOS field effect transistor representing a vertical type semiconductor device is employed to, for example, a power conversion or a power control of a motor for a vehicle or household electric appliance. The one having a super junction structure is disclosed in JP-A-11-233759 and JP-A-9-266311. The super junction structure is constituted by a structure in which a first semiconductor region of first conductive type and a second semiconductor region of second conductive type are arrayed alternately on a semiconductor substrate. This structure has a performance that exceeds a limit performance of silicon can be achieved, and is useful for achieving low resistivity in the vertical type semiconductor device.
In the super junction structure, the alternately arrayed structure of the first conductive type semiconductor region and the second conductive type semiconductor region is terminated at a semiconductor region disposed at an end of the semiconductor substrate. Therefore, a structure of an end of the alternately arrayed structure is very important. When no design is provided to that structure, in a situation where an applied voltage is larger than a withstand voltage at a connection between the first conductive type semiconductor region and the second conductive type semiconductor region, a dielectric breakdown may occur at the semiconductor region disposed at the end of the super junction structure. As a result, the performance exceeding the limit performance of silicon cannot be achieved.
An object of the invention is to provide a semiconductor device capable of withstanding high voltage.
In a semiconductor device having a vertical type element and a super junction structure on a semiconductor substrate of first conductive type, a first semiconductor region of first conductive type and a second semiconductor region of second conductive type are arrayed alternately in the super junction structure to form an element forming region and a peripheral region disposed at a periphery of the element forming region in the super junction structure. The peripheral region has an end portion constituted by the second semiconductor region. Incidentally, an electrode portion is disposed on the super junction structure. In this structure, the semiconductor substrate is electrically conducted to the first semiconductor region, the electrode is located away from the end portion while electrically conducted to the second semiconductor region disposed in the peripheral region.
According to an aspect of the present invention, a depletion layer can be expanded toward the end portion in an inside of the super junction structure. Besides, at a side of the electrode portion in the super junction structure, the depletion layer can be expanded toward the end portion. With this structure, electric concentration can be loosened at the side of the electrode portion in the super junction structure, so that withstand voltage of the semiconductor device can be improved. As a result, according to the present invention, the withstand voltage exceeds the limit in silicon.
Preferably, a third semiconductor region of second conductive type is arranged between the electrode portion and the peripheral region to electrically connect the second semiconductor region in the peripheral region and the electrode portion.
According to a second aspect of present invention, an inside of the semiconductor substrate is completely depleted by the super junction structure. Moreover, the electric field is decreased by expanding the depletion layer at the vicinity of a surface of the substrate. Therefore, the withstand voltage can be further improved.
Preferably, a fourth semiconductor region of first conductive type is disposed in the peripheral region to electrically connect each first semiconductor region located in the peripheral region. More specifically, the fourth semiconductor region of first conductive type is disposed in the second semiconductor region disposed in the peripheral region.
According to a third aspect of the present invention, in an off state of the semiconductor device, when voltage is applied to the electrode portion and the semiconductor substrate, the depletion layer is divided into a vertical electric field and a lateral electric field. A leak current is reduced by, especially, the lateral electric field in a low voltage.
Other features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings.